On-chip memory, external DRAM interfaces, and the controllers that sit above them. An interface PHY and a memory controller answer different questions.
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
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Licensable standalone last-level cache IP for a non-coherent AXI4 interface. It is not a cache-coherent NoC, not a DDR controller, and not an OTP.
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Attopsemi I-fuse is licensable OTP memory IP based on a non-explosive fuse programming mechanism. The official technology page states foundry-independent OTP without extra masks and physics-based electro-migration programming.
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Licensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionLicensable design IP. LPDDR5 and LPDDR4X PHY for a documented TSMC N7 variant. The controller is separate.
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Cyclic Design BCH ECC IP is licensable Verilog error-correction IP for SLC/MLC NAND flash controllers. The official products page lists G12–G15 core families by correction-block size with single-/multi-instance and subscription licensing options.
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Digital Blocks AXI DMA Controller IP is licensable multi-channel scatter-gather DMA soft IP for AMBA AXI4 and AXI5. The official page details configurable/fixed-channel and high-throughput SystemVerilog RTL variants with full deliverables.
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Dolphin Technology hardened Combo DDR/LPDDR PHY is licensable hard PHY IP. The official page states a silicon-proven combo PHY supporting DDR4/3/2 and LPDDR5/4x/4/3/2 up to 4266 Mbps with DFI 4.0 compliance.
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Eureka EP530 is licensable synthesizable DDR SDRAM controller IP. The official product summary states ASIC/FPGA HDL delivery and standard DDR SDRAM device support.
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Floadia LEE Flash G1 is licensable SONOS embedded Flash NVM IP for BCD processes. The official product page publishes automotive-grade specs, AEC-Q100 Grade 1 availability tables across TSMC/SMIC/GTA/SK Hynix/PSMC, and low mask-adder integration claims.
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Licensable HBM4E PHY and controller IP, published as one combined interface. GUC says it is design-ready, states speeds up to 16 Gbps, and says the PHY has taped out on TSMC N2P with CoWoS-L. GUC’s silicon-proven statement for its earlier HBM4 IP is not recorded here.
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