Public source

Eureka EP530 DDR SDRAM Controller IP

The EP530 DDR SDRAM Controller product summary reviewed on 12 November 2026 lists features including support for industry-standard Double Data Rate SDRAM from 64 Mbit to 512 Mbit devices; page-hit detection for multiple column accesses in the same row; pipeline access for continuous bursting; transferring 2 bits of data per pin with user data at twice the SDRAM data width; programmable SDRAM data width and user word size; burst lengths of 2, 4, and 8 words; programmable access timing; multiple external banks; automatic refresh with programmable intervals; self-refresh mode; programmable memory configuration registers; and an integrated data buffer synchronizing the user interface with DDR SDRAM data.

Solution category: Memory Controllers
Offering type: Product

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Overview

Eureka EP530 is licensable synthesizable DDR SDRAM controller IP. The official product summary states ASIC/FPGA HDL delivery and standard DDR SDRAM device support.

Technical capabilities

Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
DDR SDRAM controller
Numbered specification: DDR SDRAM (64Mbit–512Mbit devices stated)
DDR SDRAM (64Mbit–512Mbit devices stated) is named for this product on the reviewed page.
Recorded aliases
EP530; Eureka DDR SDRAM Controller