Public source

MLE NVMe Streamer Host Controller IP

The NVMe Streamer page reviewed on 12 November 2026 describes a Full Accelerator NVMe host subsystem integrated in FPGA programmable logic with no software in the performance path, prominently for AMD Zynq UltraScale+ MPSoC/RFSoC devices and using vendor PCIe Hard IP with GTH/GTY transceivers.

Solution category: Memory Controllers
Offering type: Product

View Official Source Find IP for your application

Overview

The official page states CPU-less NVMe host operation over PCIe Gen1–Gen4 with production license offerings.

Key features listed include one or more NVMe/PCIe host ports, PCIe enumeration, NVMe initialization/identify and queue management, control/status for IO and admin, about 50k LUTs and 170 BRAM tiles on UltraScale+, PCIe Gen1–Gen4 speeds, and x1–x8 lane scalability. Evaluation kits for Versal, UltraScale+ RFSoC/MPSoC, and Zynq-7000 are listed. Pricing table publishes Evaluation Reference Design (free, 30-day) and Production Reference Design Professional Edition starting at $24,800 with encrypted RTL under a single-project license. FAQ states block-storage (no filesystem), single namespace, and typically one SSD as PCIe endpoint. Official page shows production IP licensing with encrypted RTL deliverables.

Technical capabilities

Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
NVMe host full accelerator
Numbered specification: NVMe over PCIe Gen1–Gen4 (speeds stated on page)
NVMe over PCIe Gen1–Gen4 (speeds stated on page) is named for this product on the reviewed page.
Recorded aliases
MLE NVMe Streamer; NVMe Streamer IP

Lifecycle and categories

Lifecycle stages: Memory and subsystem IP
Solution categories: Memory Controllers
Supported versions: NVMe over PCIe Gen1–Gen4 (speeds stated on page)
Compatibility: AMD/Xilinx FPGA PCIe Hard IP + GTH/GTY; AXI4-Lite control and AXI4-Stream data per FAQ. Source