Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP

Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. Search under eMMC, SD, or SDIO resolves to this same listing.

It says the IP handles timing and interface protocol requirements for those media, processes commands in hardware, supports a single slot, and can boot directly from attached eMMC. The host interface is described as a standard 32-bit AHB bus for data and configuration, with optional AXI or OCP system/host interfaces also named in the features list. eMMC 5.1 features on the page include compliance with eMMC Specification Version 5.1, HS400 up to 400 MB/s, field firmware update, primary and alternate boot modes, and backward compatibility to 1-bit, 4-bit, and 8-bit modes. The page also lists SD Host Controller Spec v3.0 (SDXC), SDIO Spec v3.0, SD Memory Spec v3.01, and eSD Memory Spec v2.1. Deliverables listed include RTL in Verilog, UHS-I PHY GDSII, a test environment, synthesis scripts, and technical documentation. The UHS-I PHY GDSII deliverable is not published here as a separate SoC IP listing. Confirm which of SD, SDIO, and eMMC you need in the licensed configuration, and confirm the host-bus and PHY or pad options.