
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The IPM-NVMe_device page reviewed on 12 November 2026 describes an NVMe device IP core that manages data transfer between a PCIe communication interface and a NAND flash controller, off-loading the host CPU.
The official page states UNH-IOL NVM Express compliance and listing on the NVMe integrator’s list.
Features named include automatic command processing, multi-channel DMA, up to 65536 I/O queues, weighted round-robin arbitration, full NVMe register support, MSI/MSI-X, Host/Controller Memory Buffer management, and availability for PCIe Gen1 through Gen6. The page states the core is fully featured for FPGA and SoC designs and has been ported/validated on multiple AMD/Xilinx UltraScale/UltraScale+/7-series/Versal FPGAs and Lattice Certus Pro/AvantX. Reference uses include PCIe SSD with IPM-UNFC flash and IPM-BCH ECC controllers, NVMe NVRAM drives, and HBA-style products.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
NVMe device controller
Numbered specification: NVMe (UNH-IOL listed)
NVMe (UNH-IOL listed) is named for this product on the reviewed page.
Numbered specification: PCIe Gen1–Gen6 availability stated
PCIe Gen1–Gen6 availability stated is named for this product on the reviewed page.
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionLicensable design IP. DDR and LPDDR controller for LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
View solutionDigital Blocks AXI DMA Controller IP is licensable multi-channel scatter-gather DMA soft IP for AMBA AXI4 and AXI5. The official page details configurable/fixed-channel and high-throughput SystemVerilog RTL variants with full deliverables.
View solutionEureka EP530 is licensable synthesizable DDR SDRAM controller IP. The official product summary states ASIC/FPGA HDL delivery and standard DDR SDRAM device support.
View solutionMLE NVMe Streamer is licensable full-accelerator NVMe host subsystem IP for FPGAs. The official page states CPU-less NVMe host operation over PCIe Gen1–Gen4 with production license offerings.
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