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Public source

IP-Maker IPM-NVMe Device Controller IP

The IPM-NVMe_device page reviewed on 12 November 2026 describes an NVMe device IP core that manages data transfer between a PCIe communication interface and a NAND flash controller, off-loading the host CPU.

Overview

The official page states UNH-IOL NVM Express compliance and listing on the NVMe integrator’s list.

Features named include automatic command processing, multi-channel DMA, up to 65536 I/O queues, weighted round-robin arbitration, full NVMe register support, MSI/MSI-X, Host/Controller Memory Buffer management, and availability for PCIe Gen1 through Gen6. The page states the core is fully featured for FPGA and SoC designs and has been ported/validated on multiple AMD/Xilinx UltraScale/UltraScale+/7-series/Versal FPGAs and Lattice Certus Pro/AvantX. Reference uses include PCIe SSD with IPM-UNFC flash and IPM-BCH ECC controllers, NVMe NVRAM drives, and HBA-style products.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    NVMe device controller

  • Numbered specification: NVMe (UNH-IOL listed)

    NVMe (UNH-IOL listed) is named for this product on the reviewed page.

  • Numbered specification: PCIe Gen1–Gen6 availability stated

    PCIe Gen1–Gen6 availability stated is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages
Memory and subsystem IP
Solution categories
Memory Controllers
Supported versions
NVMe (UNH-IOL listed); PCIe Gen1–Gen6 availability stated
Compatibility
FPGA/SoC; validated on AMD UltraScale/Versal and Lattice platforms per page. Source

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