
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Cadence datasheet page names LPDDR5, LPDDR4X, LPDDR4, LPDDR3, DDR5, DDR4, DDR3L, and DDR3.
Single- and multi-port host interfaces and reliability and QoS features are described. The PHY is separate, and no controller-to-PHY pairing is verified. Silicon Showcase™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable DDR and LPDDR controller design IP.
Controller IP
Digital controller. The DRAM PHY is a separate product.
Finder function
memory controller
Arasan SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is one licensable multi-protocol host controller. The page says it supports SD 3.0, SDIO 3.0, and eMMC 5.1. Search under eMMC, SD, or SDIO resolves to this same listing.
View solutionArasan UFS 2.1 Host Controller IP is licensable UFS host controller IP. The page describes an M-PHY adapter layer and a UniPro link layer. The physical M-PHY is a separate offering.
View solutionDigital Blocks AXI DMA Controller IP is licensable multi-channel scatter-gather DMA soft IP for AMBA AXI4 and AXI5. The official page details configurable/fixed-channel and high-throughput SystemVerilog RTL variants with full deliverables.
View solutionEureka EP530 is licensable synthesizable DDR SDRAM controller IP. The official product summary states ASIC/FPGA HDL delivery and standard DDR SDRAM device support.
View solutionIP-Maker IPM-NVMe_Device is licensable NVMe device controller IP for PCIe SSD designs. The official page states UNH-IOL NVM Express compliance and listing on the NVMe integrator’s list.
View solutionMLE NVMe Streamer is licensable full-accelerator NVMe host subsystem IP for FPGAs. The official page states CPU-less NVMe host operation over PCIe Gen1–Gen4 with production license offerings.
View solution
