What It Is
These posts use physical AI for a system that perceives, decides, and acts on a machine such as a vehicle, robot, or drone. Both draw the same line: a wrong answer on a screen is a different failure from a wrong movement.
A Synopsys post by Dana Neustadter and Ilya Tolchinsky, dated 8 July 2026, places the security problem on the whole path from data to action. It names training data that can be incomplete or manipulated, sensors that can be degraded or spoofed, and a loss of synchronization between perception, planning, and control. It also names the silicon under that software: a hardware root of trust, a firmware update path, and IP reused across products. The post says model behavior has to be checked as conditions change. It does not name a security product, a test result, or a certification. Silicon Showcase has not certified a physical AI system from this post.
A Cadence post dated 22 October 2026 separates three networks. Inside the machine it names MIPI CSI-2, automotive SerDes or automotive Ethernet, on-chip interconnect, LPDDR, UCIe when the design uses chiplets, PCIe and CXL, and actuator networks such as time-sensitive Ethernet, EtherCAT, and CAN. It says each hop has a deadline, that a retry which reaches software can miss that deadline, and that the interfaces should support functional safety and line-rate security. It points to ISO 26262 and ASIL for vehicles and IEC 61508 and SIL for industrial systems. That is Cadence describing the requirement those interfaces are meant to help meet. It is not a certification of a listed block. Between the machine and the data center, the post describes selective upload and signed model updates, and it cites UN Regulation No. 156 and ISO 24089 for vehicle software updates. It says robotics fleets do not face the same rule yet. Inside the data center, it says UALink, Ultra Ethernet, and Ethernet for Scale-Up Networking are standards being defined. In the same post Cadence says it has UALink 200G controller and PHY IP running in 3 nm silicon, Ethernet controller IP up to 1.6T, and ESUN-ready controller IP. Those are Cadence product claims. They are not separate Silicon Showcase listings, and a product claim is not a finished standard or a demonstrated link to another vendor’s part.
Cadence also names MIPI, LPDDR, PCIe, CXL, automotive Ethernet with TSN, USB, and UCIe controller and PHY IP. Published Cadence listings that match named interfaces are the CSI-2 receiver controller, the DDR/LPDDR controller, the PCIe controller, and the UCIe controller and PHY. The published multi-speed Ethernet controller does not state TSN or automotive use. No published Cadence CXL listing was found. The published USB listing is a USB 3.0 host controller, not the USB4 service port the post also mentions.
