
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Cadence publishes the UCIe PHY in its design-IP catalog, on a page that also describes the controller.
Cadence UCIe PHY is design IP for the die-to-die physical layer.
The PHY section covers link initialization, training, power states, lane mapping, lane reversal, and scrambling. Cadence states data rates up to 32 Gbps per pin, including 4, 8, 12, 16, and 24 Gbps, for standard and advanced packages, with channel reach up to 25 mm. The page does not name a UCIe revision or a foundry process for this PHY. A 2023 tapeout announcement is a separate event and is not treated as the current data rate. A shared UCIe name does not establish compatibility with the Synopsys PHY.
PHY IP
Physical layer. Controller features on the same page are a separate listing.
Stated data rate
Provider-stated maximum on this PHY page: up to 32 Gbps per pin, including 4, 8, 12, 16, and 24 Gbps. The page does not state that this rate is available in every process, package, or configuration.
Eliyan NuLink PHY is licensable die-to-die and chip-to-chip interconnect PHY IP. The official products page states support for industry standards including UCIe and BoW on standard and advanced packaging.
View solutionSynopsys UCIe PHY IP is DesignWare die-to-die PHY IP. Synopsys states up to 64 Gb/s and 21 Tbps/mm, and compliance with the latest UCIe specification, without naming the revision.
View solutionSynopsys UCIe Controller IP is DesignWare die-to-die controller IP for the adapter and protocol layers. The provider page does not state a data rate or a numbered UCIe revision.
View solutionPortfolio listing: Synopsys UCIe IP is the combined controller, PHY, and verification IP solution. It is not a separate controller or PHY. The solution page does not name a numbered UCIe revision, and a data rate on the PHY page is not a rate for this portfolio or for every process and configuration.
View solution
