Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

Cadence UCIe PHY IP

Cadence publishes the UCIe PHY in its design-IP catalog, on a page that also describes the controller.

Overview

Cadence UCIe PHY is design IP for the die-to-die physical layer.

The PHY section covers link initialization, training, power states, lane mapping, lane reversal, and scrambling. Cadence states data rates up to 32 Gbps per pin, including 4, 8, 12, 16, and 24 Gbps, for standard and advanced packages, with channel reach up to 25 mm. The page does not name a UCIe revision or a foundry process for this PHY. A 2023 tapeout announcement is a separate event and is not treated as the current data rate. A shared UCIe name does not establish compatibility with the Synopsys PHY.

Technical capabilities

  • PHY IP

    Physical layer. Controller features on the same page are a separate listing.

  • Stated data rate

    Provider-stated maximum on this PHY page: up to 32 Gbps per pin, including 4, 8, 12, 16, and 24 Gbps. The page does not state that this rate is available in every process, package, or configuration.

Lifecycle and categories

Solution categories
UCIe IP

Related solutions

Related events

Explore promotion options