Interface IP for links off the chip and between dies. PCIe is one category. A protocol name is the category to check; it is not proof that a controller and a PHY are the same listing.
AccelerComm Polar IP is licensable 3GPP-compliant Polar encode/decode IP for 5G NR control channels. The official page states a complete TS38.212 chain for FPGA and ASIC with AXI interfaces.
View solutionAlgo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
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Analog Bits SerDes is licensable multi-protocol enterprise-class SerDes IP. The official page states PCIe Gen 3/4/5-class SerDes with silicon tape-outs in 8 nm, 7 nm, and 5 nm and customization for customer requirements.
View solutionAnalogix DisplayPort 1.1a Transmitter is licensable DisplayPort source IP. The official page states DisplayPort 1.1a compliance with HDCP and a 4-lane main link at 2.7/1.62 Gbps per lane.
View solutionArasan MIPI CSI-2 v2.1 Receiver IP is licensable camera receiver controller IP. It is the CSI-2 v2.1 receiver offering. The CSI-2 transmitter and the analog PHY are separate products on Arasan’s MIPI pages.
View solutionArasan MIPI D-PHY 1.2 Analog Transceiver IP is licensable PHY IP. The page says it can be configured as a transmitter, receiver, or transceiver, with high-speed operation up to 2.5 Gb/s per lane with deskew calibration. CSI-2 and DSI controllers are separate products.
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Atomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable CAN controller IP. The page documents Classical CAN, CAN FD, and CAN XL variants. Safety-Enhanced is an option on a stated variant, not a certification of every delivery. An analog transceiver is not included.
View solutionCAST I2C-MS is an I2C master/slave controller. The product page does not make this listing an I3C controller.
View solutionLicensable LIN controller IP. The page documents versions 1.3, 2.0, 2.1, and 2.2A, and master, slave, and combined roles. An analog transceiver is not included.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
View solutionCAST SPI-MS is an octal SPI master/slave controller. The listing does not state execute-in-place or a complete flash command set. It is not a discrete flash device.
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