Interface & Connectivity IP

PCIe IP

PCI Express controller or PHY IP. Check the generation and whether the listing is the controller, the PHY, or both.

Showing 1–10 of 10 solutions.

Cadence PCIe Controller IP
PCIe IP
Licensable design IP. PCIe controller for PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1, including endpoint configurations.
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Qualitas PCIe Gen4 to Gen6 PHY IP
PCIe IP
Qualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.
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Rambus PCIe 6.3 Controller
PCIe IP
Licensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
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Signature IP PCIe Gen 6.x / CXL 3.x / NoC IP
PCIe IP
Signature IP PCIe Gen 6.x, CXL 3.x, and NoC blocks are licensable interconnect soft IP. The official site states standalone licensing of PCIe/CXL/NoC verified RTL plus chiplet design services using the same blocks.
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Silicon Interfaces PCIe 3.0 Controller IP
PCIe IP
Silicon Interfaces PCIe 3.0 Controller IP is a licensable synthesizable RTL PCI Express controller core. The official AssetsPCIe page states a fully synthesizable Verilog HDL core with UVM testbench and optional VIP add-ons.
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Socionext PCIe / DDR / USB / HBM IP Macros
PCIe IP
Socionext IP Macros are a foundry/node-mapped lineup of interface and memory macros including PCIe RT/EP, DDR4/5, LPDDR4/5, HBM2/3, USB, Ethernet MAC, and MIPI DSI/CSI. The official Line-up of IP Macro page presents availability tables across 65 nm through 3 nm classes.
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Synopsys Controller IP for PCI Express 6.x
PCIe IP
Licensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
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Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0
PCIe IP
Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0 is DesignWare PHY IP. The reviewed page says it supports the required features of the PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, plus PIPE and CXL 1.0, 1.1, and 2.0. It is not a PCIe controller.
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Terminus Circuits PCIe PHY IP
PCIe IP
Terminus Circuits PCIe PHY IP is licensable PIPE-compliant PCI Express physical-layer IP. The official IP portfolio page lists PCIe Gen2–Gen5 PHY SKUs with TSMC node options, retimer offerings, and hard-IP deliverables.
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XtremeSilica PCIe Gen4/5/6 Controller IP Portfolio
PCIe IP
XtremeSilica PCIe controller IP covers Gen4/5/6 offerings in its silicon IP portfolio. The official portfolio page states validated high-speed IP cores with Gen5 at 32 GT/s, Gen4 at 16 GT/s, and Gen6 at 64 GT/s PAM4, with AXI/AHB integration notes.
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