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Terminus Circuits PCIe PHY IP

The IP Portfolio page reviewed on 12 November 2026 presents Terminus Circuits PCIe PHY under PCI Express PHY with PCIe 4.0/3.0/2.0 PHY described as low-latency, small form-factor, and PIPE4.3 compliant.

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Overview

Terminus Circuits PCIe PHY IP is licensable PIPE-compliant PCI Express physical-layer IP. The official IP portfolio page lists PCIe Gen2–Gen5 PHY SKUs with TSMC node options, retimer offerings, and hard-IP deliverables.

Key features named include quad PCIe 16/8/5/2.5 Gbps per lane, on-chip termination calibration, 3-tap Tx FIR and CTLE up to 12 dB, CDR and 3-tap Rx DFE, bifurcation/quadfurcation, SRnS support and ESD structures, wide temperature −40°C to +125°C, programmable loopback, and auto calibration. Separate callouts name PCIe Gen5 at 32 Gbps on TSMC 12 nm FFC, PCIe Gen4 at 16 Gbps on multiple nodes, and a multi-rate 2.5G–16G PCIe Retimer. Portfolio deliverables listed include user/integration guides, netlist and timing library, register map and Verilog, IBIS-AMI models, LEF, LVS/DRC reports, and silicon-proven data. Adjacent USB, MIPI M-PHY, multi-standard SerDes, Ethernet PHY, and PLL line items appear on the same page but are separate offerings from this PCIe PHY listing. Contact block lists Bangalore, India.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

  • Finder function

    PCIe PHY

  • Numbered specification: PIPE4.3 stated for Gen2–4 family

    PIPE4.3 stated for Gen2–4 family is named for this product on the reviewed page.

Lifecycle and categories

Solution categories
PCIe IP
Supported versions
PCIe Gen2–Gen5 (2.5/5/8/16/32 Gbps); PIPE4.3 stated for Gen2–4 family
Compatibility
TSMC nodes named for PCIe Gen5 (12 nm FFC) and lower gens (including 28HPC/HPC+, 65GP, 55LP); GF nodes listed for related SerDes rates. Source

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