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Public source

Qualitas PCIe Gen4 to Gen6 PHY IP

The Qualitas Semiconductor English home and portfolio pages reviewed on 12 November 2026 present PCI Express PHY IP Gen4 to Gen6 as a flagship interconnect offering, stating delivery up to 64 GT/s per lane with low-latency positioning for AI, HPC, and data-center applications.

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Overview

Qualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.

The same site lists related high-speed interconnect IP including 100G/50G/20G SerDes PHY, die-to-die UCIe PHY, camera/display MIPI interface IP, and USB and Ethernet PHY IP. Public company materials describe silicon experience and foundry partnership context. Controllers are not the subject of this PHY listing. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

  • Finder function

    PCIe PHY

  • Numbered specification: PCIe Gen4 to Gen6 (up to 64 GT/s stated)

    PCIe Gen4 to Gen6 (up to 64 GT/s stated) is named for this product on the reviewed page.

Lifecycle and categories

Solution categories
PCIe IP
Supported versions
PCIe Gen4 to Gen6 (up to 64 GT/s stated)
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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CXL IP

Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0 is DesignWare PHY IP. The reviewed page says it supports the required features of the PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, plus PIPE and CXL 1.0, 1.1, and 2.0. It is not a PCIe controller.

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Terminus Circuits PCIe PHY IP

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Terminus Circuits PCIe PHY IP is licensable PIPE-compliant PCI Express physical-layer IP. The official IP portfolio page lists PCIe Gen2–Gen5 PHY SKUs with TSMC node options, retimer offerings, and hard-IP deliverables.

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Rambus PCIe 6.3 Controller

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Licensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.

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Signature IP PCIe Gen 6.x / CXL 3.x / NoC IP

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Signature IP PCIe Gen 6.x, CXL 3.x, and NoC blocks are licensable interconnect soft IP. The official site states standalone licensing of PCIe/CXL/NoC verified RTL plus chiplet design services using the same blocks.

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Silicon Interfaces PCIe 3.0 Controller IP

PCIe IP

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