
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Signature IP home page reviewed on 12 November 2026 states 'IP you license.
Signature IP PCIe Gen 6.x, CXL 3.x, and NoC blocks are licensable interconnect soft IP. The official site states standalone licensing of PCIe/CXL/NoC verified RTL plus chiplet design services using the same blocks.
It claims 30+ IP blocks available, Gen 5 PCI-SIG certification, CXL Consortium membership, and 32+ successful SoC projects. Standalone IP blocks named include PCIe 6.x, CXL 3.x, coherent and non-coherent NoC, SysWare, and peripherals as verified RTL. The same blocks underpin custom Compute, IO, and Memory Expander chiplet engagements. Confirm the exact revision, role, and deliverables on the current provider page before integration.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
PCIe / CXL / NoC
Numbered specification: PCIe Gen 6.x
PCIe Gen 6.x is named for this product on the reviewed page.
Numbered specification: CXL 3.x
CXL 3.x is named for this product on the reviewed page.
Numbered specification: C-NoC / NC-NoC
C-NoC / NC-NoC is named for this product on the reviewed page.
Recorded aliases
SignatureIP PCIe 6; SigIP NoC; Signature IP CXL
Licensable design IP. PCIe controller for PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1, including endpoint configurations.
View solutionQualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.
View solutionLicensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
View solutionSilicon Interfaces PCIe 3.0 Controller IP is a licensable synthesizable RTL PCI Express controller core. The official AssetsPCIe page states a fully synthesizable Verilog HDL core with UVM testbench and optional VIP add-ons.
View solutionSocionext IP Macros are a foundry/node-mapped lineup of interface and memory macros including PCIe RT/EP, DDR4/5, LPDDR4/5, HBM2/3, USB, Ethernet MAC, and MIPI DSI/CSI. The official Line-up of IP Macro page presents availability tables across 65 nm through 3 nm classes.
View solutionLicensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
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