
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Line-up of IP Macro page reviewed on 12 November 2026 states that Socionext's IP macros with proven track records support customers in advanced SoC development.
The official Line-up of IP Macro page presents availability tables across 65 nm through 3 nm classes.
High Speed Interface Macros table marks availability by process class (65/55, 40, 28/22, 16/12, 7/6, 5, 3 nm) for USB; Ethernet MAC; HDMI / V-By-One / FPD-Link; LVDS / SubLVDS; MIPI DSI/CSI; PCIe RT/EP; SATA; UFS; DDR4/DDR5; LPDDR4/LPDDR5; and HBM2/HBM3. Functional/Interface Macros also list Arm cores, Mali-G, JPEG/H.264/H.265 image cores, SHA/PKA and AES/DES security cores, and SPI/UART/eMMC/SD controllers. Analog Macros cover ADC, DAC, AFE, temperature sensor, and PLL; RF Macros list Bluetooth, Zigbee, and WiFi on selected nodes. This listing focuses on the high-speed interface and memory macros (PCIe, DDR/LPDDR/HBM, USB) called out in the candidate title; other lineup rows are separate macros on the same page.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Numbered specification: PCIe RT/EP
PCIe RT/EP is named for this product on the reviewed page.
Numbered specification: DDR4/DDR5
DDR4/DDR5 is named for this product on the reviewed page.
Numbered specification: LPDDR4/LPDDR5
LPDDR4/LPDDR5 is named for this product on the reviewed page.
Numbered specification: HBM2/HBM3
HBM2/HBM3 is named for this product on the reviewed page.
Numbered specification: USB
USB is named for this product on the reviewed page.
Numbered specification: Ethernet MAC
Ethernet MAC is named for this product on the reviewed page.
Numbered specification: MIPI DSI/CSI (node-dependent per table)
MIPI DSI/CSI (node-dependent per table) is named for this product on the reviewed page.
Licensable design IP. PCIe controller for PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1, including endpoint configurations.
View solutionQualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.
View solutionLicensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
View solutionSignature IP PCIe Gen 6.x, CXL 3.x, and NoC blocks are licensable interconnect soft IP. The official site states standalone licensing of PCIe/CXL/NoC verified RTL plus chiplet design services using the same blocks.
View solutionSilicon Interfaces PCIe 3.0 Controller IP is a licensable synthesizable RTL PCI Express controller core. The official AssetsPCIe page states a fully synthesizable Verilog HDL core with UVM testbench and optional VIP add-ons.
View solutionLicensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
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