
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
This is the controller listing.
Licensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles.
It does not include a PHY, and the transfer rate is stated in GT/s rather than as useful data throughput.
Finder function
PCIe controller
Numbered specification
6.2, 6.1, 6.0.1, 5.0, 4.0, 3.1
Configuration checks
Confirm the exact revision, lane configuration, and role. Do not read 64 GT/s as 64 Gb/s of useful throughput, and do not treat this listing as a PHY.
Recorded aliases
Synopsys PCIe 6 controller
Licensable design IP. PCIe controller for PCIe 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1, including endpoint configurations.
View solutionLicensable PCIe controller IP. The page documents PCIe 6.3 with revisions 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
View solutionSilicon Interfaces PCIe 3.0 Controller IP is a licensable synthesizable RTL PCI Express controller core. The official AssetsPCIe page states a fully synthesizable Verilog HDL core with UVM testbench and optional VIP add-ons.
View solutionXtremeSilica PCIe controller IP covers Gen4/5/6 offerings in its silicon IP portfolio. The official portfolio page states validated high-speed IP cores with Gen5 at 32 GT/s, Gen4 at 16 GT/s, and Gen6 at 64 GT/s PAM4, with AXI/AHB integration notes.
View solutionQualitas PCIe PHY IP is licensable hard PHY IP covering PCI Express Gen4 through Gen6. The official English site states PCIe PHY delivering up to 64 GT/s per lane alongside UCIe, SerDes, MIPI, USB, and Ethernet PHY lines.
View solutionSignature IP PCIe Gen 6.x, CXL 3.x, and NoC blocks are licensable interconnect soft IP. The official site states standalone licensing of PCIe/CXL/NoC verified RTL plus chiplet design services using the same blocks.
View solution
