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United States|Sunnyvale (HQ)
Electronic design automation and semiconductor IP company that publishes die-to-die interface IP, including UCIe controller, PHY and verification IP.
25 published solutions.
Synopsys MIPI CSE 2.0 Security Module is licensable interface security IP for MIPI CSI-2 streams. The official page states support for MIPI Camera Service Extensions CSE 2.0 with inline integrity protection and optional encryption, and says it integrates with Synopsys CSI-2 Host Controllers.
Licensable CXL controller IP. The product page documents device, host, switch, and dual-mode ports, and CXL 4.0 at 128 GT/s with backward compatibility to CXL 3.x, 2.0, and 1.x. The PCIe 5.0/CXL PHY, the IDE modules, and verification IP are not this listing.
Synopsys MIPI DSI/DSI-2 Host Controller IP is the display-output host role. The PHY, including C-PHY or D-PHY, is separate. This listing is not a MIPI CSI-2 camera receiver, not a GPU, and not a PHY-only block.
Licensable controller IP for PCI Express. The page documents revisions 6.2, 6.1, 6.0.1, 5.0, 4.0, and 3.1, a 64 GT/s transfer rate, and endpoint, root, switch, and dual-mode roles. A PHY is not included.
Licensable DDR5 and DDR4 PHY IP. The page documents up to 8400 Mb/s, DFI 5.0, and a hard PHY. A memory controller is not included.
Licensable design IP. Digital Ethernet MAC for 1 Gb/s, 2.5 Gb/s, 5 Gb/s, and 10 Gb/s. The PHY is a separate product.
Licensable design IP. Ethernet physical coding sublayer for 1 Gb/s, 2.5 Gb/s, 5 Gb/s, and 10 Gb/s. This is not an Ethernet MAC.
Licensable design IP. Digital Ethernet MAC with documented configurations at 1 Gb/s, 2.5 Gb/s, 5 Gb/s, 10 Gb/s, 25 Gb/s, 40 Gb/s, 50 Gb/s, and 100 Gb/s.
Licensable design IP. Digital memory controller for LPDDR5X, LPDDR5, and LPDDR4X. The PHY is separate.
Licensable design IP. Multi-protocol SerDes PHY. The provider states a serial lane-rate range; that lane rate is not an Ethernet line rate.
Licensable design IP. USB 3.2 controller with documented device support. Host and dual-role support are not documented.
Synopsys DDR5/4 Controller IP is DesignWare memory-controller IP. The reviewed page says it supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs and connects to a PHY through DFI 5.0. It is not the DDR PHY.
