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Public source

Synopsys CXL 4.0 Controller IP

The Synopsys CXL Controller IP page reviewed on 9 November 2026 describes port logic for a CXL device, host, or switch, including dual-mode selection between device and host.

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Overview

Those rates are provider-stated and were not remeasured.

The same page describes optional Integrity and Data Encryption modules for CXL 2.0, 3.x, and 4.0, and TDISP or TSP support, as security options used with the controller. Those modules are not separate catalog rows in this batch, and they are not the controller itself. The published Synopsys PHY for PCI Express 5.0 and CXL 2.0/1.0 remains a different listing. The page also says the controller can support PCI Express 7.0 when a PCIe SerDes PHY is used. That statement is not stored as a PCIe generation on this controller. No process node is stated as a complete set.

Technical capabilities

  • Numbered specification

    CXL 4.0

  • Finder function

    CXL controller

  • Recorded aliases

    Synopsys CXL Controller; DesignWare CXL Controller

  • Configuration checks

    IDE security modules and CXL verification IP are not this listing. Do not read the PCIe 5.0/CXL PHY as this controller.

Lifecycle and categories

Solution categories
CXL IP
Supported versions
CXL 4.0
Compatibility
CXL 4.0 with backward compatibility to CXL 3.x, 2.0, and 1.x, as stated on the Synopsys CXL Controller IP page. Source

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Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0

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Synopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0 is DesignWare PHY IP. The reviewed page says it supports the required features of the PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, plus PIPE and CXL 1.0, 1.1, and 2.0. It is not a PCIe controller.

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