NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Rambus CXL 3.1 Controller
Use this listing for the controller protocol and the documented CXL.io, CXL.cache, and CXL.mem features.
- Solution category: CXL IP
- Offering type: Product
Overview
The page documents CXL 3.1, backward compatibility with CXL 2.0 and CXL 1.1, CXL.io, CXL.cache, and CXL.mem, and 64 GT/s. It is not a finished memory expander and does not include a PHY.
Device type, capacity, and the physical interface still need their own evaluation.
Technical capabilities
Published as design IP
Licensable CXL controller IP.
Finder function
CXL controller
Numbered specification
CXL 3.1, CXL 2.0, CXL 1.1
Configuration checks
Confirm CXL.io, CXL.cache, CXL.mem, and the device type you need. This listing is not a finished memory expander and not a PHY.
Recorded aliases
Rambus CXL 3.1 controller
Lifecycle and categories
- Lifecycle stages
- Interface and connectivity IP
- Solution categories
- CXL IP
- Supported versions
- 3.1, 2.0, 1.1
- Compatibility
- Pricing, licensing, and configuration availability require provider confirmation. Source
Related solutions
Synopsys CXL 4.0 Controller IP
CXL IPLicensable CXL controller IP. The product page documents device, host, switch, and dual-mode ports, and CXL 4.0 at 128 GT/s with backward compatibility to CXL 3.x, 2.0, and 1.x. The PCIe 5.0/CXL PHY, the IDE modules, and verification IP are not this listing.
View solutionSynopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0
CXL IPSynopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0 is DesignWare PHY IP. The reviewed page says it supports the required features of the PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, plus PIPE and CXL 1.0, 1.1, and 2.0. It is not a PCIe controller.
View solutionRelated events
NOV192026
Workshop
SystemC Evolution Day 2026
- November 19, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative