Interface & Connectivity IP
Compute Express Link IP. A PCIe PHY that also names CXL belongs here only when the source states CXL, not because the protocols share a connector.
Licensable CXL controller IP. The page documents CXL 3.1, backward compatibility with CXL 2.0 and CXL 1.1, CXL.io, CXL.cache, and CXL.mem, and 64 GT/s. It is not a finished memory expander and does not include a PHY.
View solutionLicensable CXL controller IP. The product page documents device, host, switch, and dual-mode ports, and CXL 4.0 at 128 GT/s with backward compatibility to CXL 3.x, 2.0, and 1.x. The PCIe 5.0/CXL PHY, the IDE modules, and verification IP are not this listing.
View solutionSynopsys PHY IP for PCI Express 5.0 and CXL 2.0/1.0 is DesignWare PHY IP. The reviewed page says it supports the required features of the PCIe 5.0, 4.0, 3.1, 2.1, and 1.1 specifications, plus PIPE and CXL 1.0, 1.1, and 2.0. It is not a PCIe controller.
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