Interface & Connectivity IP
Ethernet controller or PHY IP. Match the speed the listing states. A PCS listing and a SerDes block are not Ethernet MAC listings.
Algo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
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Atomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
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Licensable design IP. Soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s, including MAC, PCS, and DMA functions.
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Chevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
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Comcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.
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CoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.
View solutionCoreTSE_AHB is triple-speed Ethernet MAC IP for supported Microchip FPGAs, with an AMBA AHB initiator and an integrated DMA engine. The page documents 10 Mb/s, 100 Mb/s, and 1 Gb/s. The PHY stays external, through G/MII or a ten-bit interface. This is not the CoreTSE configuration, which does not document that AHB and DMA path. Both cores are included in the CoreTSE_AHB license.
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Realtek Ethernet Total Solutions is a wired-connectivity PHY and controller platform, currently evidenced by live 2.5GbE product pages.
View solutionLicensable 10/100 Ethernet PHY IP with EtherCAT support for industrial networking SoCs.
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Intilop Ethernet/TCP IP cores are licensable networking soft IP for FPGA and ASIC. The official site highlights a full TCP/UDP stack in hardware with true 10G/40G line-rate SmartNIC performance and IP core product listings.
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SOC-E ETSN is licensable Time-Sensitive Networking endpoint IP for FPGA. The official product page states 100M/1G/10G TSN endpoint support with IEEE 802.1AS/Qav/Qbv/Qci/CB/Qcc features and synthesizable configurability.
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