Silicon Showcase⁠™

Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

Atomic Rules UDP Offload Engine FPGA IP Core

The UDP Offload Engine page reviewed on 12 November 2026 describes a UDP FPGA IP Core for immediate operation at 10, 25, 40, 50, 100, or 400 GbE.

View Official Source (opens in a new tab)Find IP for your application

Overview

Atomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP.

It states implementation of UDP/IPv4 standard RFC 768/791 including checksum, segmentation, and reassembly hardware offload, tested with popular FPGA vendors’ GbE Ethernet MACs. Features listed include concurrent send/receive, programmable Ethernet MTU up to 16K bytes, UDP PDU up to the IPv4 64K limit, 16-entry ARP cache (RFC 826), ICMP echo response for ping, IEEE 802.1Q VLAN, Layer-3 direct mode, control-plane statistics, low-area multi-instance design, and Avalon and AXI4 interfaces. A datasheet PDF download is offered. Address 287 Chester Rd, Auburn, NH 03032 is listed.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    UDP/IP offload

  • Numbered specification: UDP/IPv4 RFC 768/791

    UDP/IPv4 RFC 768/791 is named for this product on the reviewed page.

  • Recorded aliases

    Atomic Rules UOE; UDP Offload Engine IPv4

Lifecycle and categories

Solution categories
Ethernet IP
Supported versions
UDP/IPv4 RFC 768/791; 10/25/40/50/100/400 GbE
Compatibility
Works with FPGA vendor GbE MACs; Avalon and AXI4 interfaces. Source

Related solutions

Algo-Logic ULL 10GE MAC + PHY IP

Ethernet IP

Algo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.

View solution

CAST LLEMAC-1G

Ethernet IP

Licensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.

View solution

Cadence Multi-Speed Ethernet Controller IP

Ethernet IP

Licensable design IP. Soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s, including MAC, PCS, and DMA functions.

View solution

Chevin Technology 10/25/40/100G Ethernet MAC/PCS IP

Ethernet IP

Chevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.

View solution

Comcores Ethernet Controller IP (10M–10G)

Ethernet IP

Comcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.

View solution

CoreTSE

Ethernet IP

CoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.

View solution

Related events

Explore promotion options