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CoreTSE

Full duplex is documented at 10 Mb/s, 100 Mb/s, and 1 Gb/s.

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Overview

CoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.

The page also names MDIO access to PHY registers, jumbo frames, and PAUSE flow control. It does not state a host bus or a DMA engine for this core; those are CoreTSE_AHB. No Ethernet line rate above 1 Gb/s is documented. The supported FPGA families, frame size, and licensed deliverable need confirmation.

Technical capabilities

  • Controller IP

    Digital MAC. The external PHY is not included.

  • Finder function

    Ethernet MAC

  • Implementation target

    Supported Microchip FPGAs

  • Configuration checks

    Confirm the FPGA family and the PHY-side interface. Do not treat CoreTSE_AHB as this same configuration.

  • Recorded aliases

    CoreTSE; triple-speed Ethernet MAC

Lifecycle and categories

Solution categories
Ethernet IP
Compatibility
Pricing, licensing, and configuration availability require provider confirmation. Source

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