
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Ethernet Controller page reviewed on 12 November 2026 describes an ASIC-proven, feature-rich network interface integrating DMA, MAC, timestamping, and a software stack.
Comcores Ethernet Controller is licensable ASIC-proven network interface IP.
Controllers ranging from 10M to 10GbE are stated, with single or multi-port configurations and IEEE Ethernet compliance. Key capabilities listed include IEEE 802.3 MAC at 10M/100M/1G/2.5G/10G; IEEE 802.1AS gPTP and IEEE 1588v2 hardware timestamping with sub-microsecond accuracy; integrated DMA; host interfaces PCIe x1/x2/x4, RGMII, RMII, SGMII, and SPI; optional IEEE 802.1AE MACsec; VLAN/QoS (802.1Q); and Linux/Windows/RTOS drivers with TSN/AVB framework support. Deliverables include bespoke RTL (source or encrypted), documentation, simulation environment, register specification, and SDC timing constraints. Official page confirms ASIC-proven IP with RTL licensing deliverables.
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
Ethernet MAC/controller
Numbered specification: IEEE 802.1AS
IEEE 802.1AS is named for this product on the reviewed page.
Numbered specification: IEEE 1588v2
IEEE 1588v2 is named for this product on the reviewed page.
Numbered specification: optional 802.1AE
optional 802.1AE is named for this product on the reviewed page.
Licensable design IP. Soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s, including MAC, PCS, and DMA functions.
View solutionAlgo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
View solutionAtomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
View solutionChevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
View solutionCoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.
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