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Chevin Technology 10/25/40/100G Ethernet MAC/PCS IP

The MAC/PCS page reviewed on 12 November 2026 describes a low-latency 10/25/40/100Gbit/s Ethernet MAC with example latency/resource figures (for example 44.8 ns / 2749 LUTs at 10G; 20.5 ns / 2680 LUTs at 25G) and combined MAC+PCS round-trip figures.

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Overview

Chevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.

It states design to IEEE 802.3by, CRC32 FCS checker/generator, pause packets, deficit idle control, store-and-forward and cut-through modes, statistics counters, fault handling, and MAC filter/promiscuous mode. Options include AMD/Xilinx AXI4-Stream, VLAN 802.1Q & PFC, IEEE 1588, advanced filters, and encrypted netlist. A companion 10/25/40/100G PCS/PMA block is described with 64b66b codec, scrambler, gearbox, BER monitoring, and PRBS. Target platforms named include Altera Agilex and AMD Virtex UltraScale, with reference boards from Bittware and Alpha Data. Flexible licensing terms are stated. Address The Bradfield Centre, Cambridge CB4 0GA is listed.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • Controller IP

    Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.

  • Finder function

    Ethernet MAC/PCS

  • Numbered specification: IEEE 802.3by

    IEEE 802.3by is named for this product on the reviewed page.

  • Recorded aliases

    Chevin MAC/PCS; Chevin 25G Ethernet MAC

Lifecycle and categories

Solution categories
Ethernet IP
Supported versions
10/25/40/100G Ethernet; IEEE 802.3by
Compatibility
Altera Agilex and AMD UltraScale FPGAs; AXI4-Stream option; SFP28 path via 25GPCS. Source

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