
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Cadence brochure, dated November 2022, describes a soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s.
Its architecture includes a MAC, 1000BASE-X/USXGMII PCS, and DMA. The analog PHY is not included. Silicon Showcase™ reviewed the brochure on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable Ethernet controller design IP.
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Ethernet MAC
Comcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.
View solutionAlgo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
View solutionAtomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
View solutionChevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
View solutionCoreTSE is triple-speed Ethernet MAC IP for supported Microchip FPGAs. The page documents operation at 10 Mb/s, 100 Mb/s, and 1 Gb/s, which it also writes as 10/100/1000 Mbps. The PHY connects through G/MII or an SGMII ten-bit interface and stays a separate part. CoreTSE_AHB is a distinct AHB and DMA configuration. Both cores are included in the CoreTSE_AHB license, and this listing is only CoreTSE.
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