EDA & Design Tools

Tools for designing and verifying your SoC. A listing states foundry, package, or another vendor’s IP support only when that page says so.

Simulate
Run logic and system simulation.
Simulation
Verify formally
Check named properties with a formal tool.
Formal verification
Emulate
Exercise a design on an emulation system, not a wafer shuttle.
Emulation
Synthesis & DFT
Synthesize logic, and add scan or BIST when a listing covers DFT, not automated test equipment.
Synthesis DFT
Implement
Place and route the physical implementation.
Physical design
Sign off
Close timing and physical checks such as DRC and LVS.
Timing DRC and LVS