NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Synopsys VCS
Synopsys describes VCS as a functional verification solution for complex SoCs.
Overview
It is an EDA tool, not design IP.
The product page lists SystemVerilog support, a native testbench, verification planning, coverage analysis, and integration with Verdi debug, VC Formal, and verification IP. It also describes simulation acceleration with ZeBu. Performance claims on the page were not independently measured. Process support and license terms are not stated on the page reviewed on 25 October 2026.
Lifecycle and categories
- Lifecycle stages
- Functional verification
- Solution categories
- Simulation
Official resources
Related solutions
Cadence Xcelium Logic Simulator
SimulationCadence Xcelium is a logic simulator for SystemVerilog, VHDL, SystemC, e, UVM, mixed-signal, and low-power verification. It is an EDA tool, not design IP.
View solutionSiemens Questa One
Formal VerificationSiemens Questa One is a verification suite whose page names simulation, debug, static, and formal engines. Individual engines are not separated here.
View solutionRelated events
NOV192026
Workshop
SystemC Evolution Day 2026
- November 19, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative