Verification IP, emulation, formal verification and simulation.
Aldec Verification IP is licensable VIP for industry-standard interfaces. The official VIP solutions page describes Transactors, Monitors, and Speed Adapters for USB, PCIe, AXI, AHB, OCB, and Gb Ethernet with SCE-MI co-emulation support.
View solutionBreker Trek Suite and SystemVIP are Portable Stimulus verification products and scenario VIP libraries. Official home and Trek Suite pages describe PSS-based test generation across simulation, emulation and silicon.
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Cadence Jasper is a formal and static verification platform for RTL and C/C++. It is an EDA tool, not an architecture-modeling product listing.
View solutionCadence Palladium is a family of hardware emulation systems. Capacity figures belong to the named variant, not to every configuration.
View solutionCadence Xcelium is a logic simulator for SystemVerilog, VHDL, SystemC, e, UVM, mixed-signal, and low-power verification. It is an EDA tool, not design IP.
View solutionSiemens Questa One is a verification suite whose page names simulation, debug, static, and formal engines. Individual engines are not separated here.
View solutionSiemens Veloce Strato CS is an emulation platform. Its stated capacity is a scaling range, not the capacity of every configuration.
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SmartDV MIPI M-PHY VIP is verification IP for the MIPI M-PHY physical layer. The product page labels it Verification IP, not design/silicon PHY IP. It states compliance with MIPI M-PHY v6.0 and backward compatibility with v5.0, v4.1, and v3.0.
View solutionSynopsys VC Formal is a formal verification tool for SoC RTL, including property, connectivity, register, and equivalence apps. It is an EDA tool, not design IP.
View solutionSynopsys VCS is a functional-verification simulator with SystemVerilog and UVM support, coverage, and debug integration. It is an EDA tool, not design IP.
View solutionSynopsys ZeBu-200 is a hardware emulation platform for long-running RTL, software, and power workloads. It is an emulation system, not a multi-project wafer shuttle.
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Truechip UFS 5.0 Verification IP is VIP for JEDEC UFS host/device verification. The official page states compliance with UFS 5.0/4.0/3.1/3.0 and native SystemVerilog UVM/OVM/VMM deliverables.
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