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Public source

Aldec Verification IP (PCIe / USB / AXI / Ethernet)

The Verification IP page reviewed on 12 November 2026 explains VIP as Bus Functional Model plus test-harness modules connecting ASIC/SoC interfaces to the testbench.

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Overview

Aldec Verification IP is licensable VIP for industry-standard interfaces.

It categorizes Aldec VIP as Transactors (message-level inject/respond with error injection), Monitors (read-only protocol capture to higher-level messages), and Speed Adapters (synchronize emulator clocks to real external devices). Named interface coverage includes USB, PCIe, AXI, AHB, OCB, Gb Ethernet and others. Interfaces are stated in SystemVerilog or C++ for UVM simulation or SystemC virtual platforms, with Accellera SCE-MI adherence so transactors/monitors work in simulation or emulation. Availability is via the VIP/IP Core product database; custom VIP services are offered when a configuration is missing.

Technical capabilities

  • Published as design IP

    Verification IP for simulation and validation. This listing is not a finished chip.

  • Verification IP

    Verification IP. This is not design/silicon IP for integration into an SoC RTL netlist as a PHY or controller.

  • Numbered specification: USB, PCIe, AXI, AHB, OCB, Gb Ethernet VIP variants as listed on page

    USB, PCIe, AXI, AHB, OCB, Gb Ethernet VIP variants as listed on page is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages
Functional verification
Solution categories
Verification IP
Supported versions
USB, PCIe, AXI, AHB, OCB, Gb Ethernet VIP variants as listed on page
Compatibility
SystemVerilog or C++; UVM or SystemC; SCE-MI co-emulation stated. Source

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SmartDV MIPI M-PHY VIP

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SmartDV MIPI M-PHY VIP is verification IP for the MIPI M-PHY physical layer. The product page labels it Verification IP, not design/silicon PHY IP. It states compliance with MIPI M-PHY v6.0 and backward compatibility with v5.0, v4.1, and v3.0.

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Truechip UFS 5.0 Verification IP

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Truechip UFS 5.0 Verification IP is VIP for JEDEC UFS host/device verification. The official page states compliance with UFS 5.0/4.0/3.1/3.0 and native SystemVerilog UVM/OVM/VMM deliverables.

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