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Public source

SmartDV MIPI M-PHY VIP

The MIPI M-PHY VIP product page reviewed on 12 November 2026 describes SmartDV MIPI M-PHY Verification IP for verifying the M-PHY physical layer across operating modes, gear configurations, and interface types.

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Overview

It states compliance with MIPI M-PHY v6.0 and backward compatibility with v5.0, v4.1, and v3.0.

Documented support includes serial and protocol-layer interfaces, Type-I and Type-II operations, PWM gears 0 through 7, HS gears 1 through 4, multi-lane configurations with inter-lane skew insertion and detection, and M-PHY Serial and RMMI interfaces with bus widths of 10, 20, 40, 80, and 160 bits per lane. The page says the VIP supports UVM, OVM, VMM, SystemVerilog, and Verilog, and names compatibility with major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator. This listing is VIP only; SmartDV design IP products are separate. Confirm the exact revision, role, and deliverables on the current provider page before integration.

Technical capabilities

  • Published as design IP

    Verification IP for simulation and validation. This listing is not a finished chip.

  • Verification IP

    Verification IP. This is not design/silicon IP for integration into an SoC RTL netlist as a PHY or controller.

  • Finder function

    MIPI M-PHY VIP

  • Numbered specification: MIPI M-PHY v6.0

    MIPI M-PHY v6.0 is named for this product on the reviewed page.

  • Numbered specification: backward compatible with v5.0, v4.1, v3.0

    backward compatible with v5.0, v4.1, v3.0 is named for this product on the reviewed page.

Lifecycle and categories

Lifecycle stages
Functional verification
Solution categories
Verification IP
Supported versions
MIPI M-PHY v6.0; backward compatible with v5.0, v4.1, v3.0
Compatibility
Confirm configuration, process support, and companion IP with the provider. Companion PHY or controller products are separate listings unless the reviewed page states a bundle. Source

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