Public source

Breker Trek SoC Verification Platform / SystemVIP

The Breker home page reviewed on 12 November 2026 presents SystemVIP scenario libraries (System Coherency, RISC-V CoreAssurance, RISC-V SoCReady, Arm SoCReady, Security HRoT, Power Management, Networking Gen, Performance Profiling) plus Trek Suite products and scenario modeling (Intent Specification, Portable Stimulus, Native C++).

Solution category: Verification IP
Offering type: Product

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Overview

Official home and Trek Suite pages describe PSS-based test generation across simulation, emulation and silicon.

The Trek Suite overview states TrekUVM generates UVM test cases from scenario models, while TrekSoC and TrekSoC-Si generate SoC tests including stimulus, expected results and coverage for simulation/emulation/prototyping/silicon reuse based on Accellera PSS. Phone +1.408.890.7146 and info@brekersystems.com are listed. The offering is verification platform/VIP content rather than RTL design IP.

Technical capabilities

Published as design IP
Verification IP for simulation and validation. This listing is not a finished chip.
Verification IP
Verification IP. This is not design/silicon IP for integration into an SoC RTL netlist as a PHY or controller.
Finder function
PSS / SoC verification VIP
Recorded aliases
Breker Trek; TrekSoC; SystemVIP; Breker TrekUVM

Lifecycle and categories

Lifecycle stages: Functional verification
Solution categories: Verification IP
Supported versions: PSS-based TrekUVM / TrekSoC / TrekSoC-Si; SystemVIP libraries as listed
Compatibility: Simulation, emulation, prototyping and silicon reuse stated; UVM transactional testbenches for TrekUVM. Source