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Synopsys VC Formal

The Synopsys VC Formal page describes formal analysis for control and datapath, with apps for automatic extracted properties, connectivity checking, register verification, sequential equivalence, formal property verification, security, low power, datapath validation, and functional safety.

View Official Source (opens in a new tab)Browse Formal Verification

Overview

Synopsys VC Formal is a formal verification tool for SoC RTL, including property, connectivity, register, and equivalence apps.

It states native integration with VCS and Verdi. Which apps are included in a given license, and whether a design can be signed off formally, need confirmation from Synopsys.

Lifecycle and categories

Lifecycle stages
Functional verification
Solution categories
Formal Verification

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Siemens Questa One is a verification suite whose page names simulation, debug, static, and formal engines. Individual engines are not separated here.

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