Silicon Showcase⁠™

Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

Cadence Xcelium Logic Simulator

The Xcelium page, reviewed on 25 October 2026, describes a logic simulator with support for SystemVerilog, VHDL, SystemC, e, UVM, mixed-signal, low power, and X-propagation.

View Official Source (opens in a new tab)Browse Simulation

Overview

It is an EDA tool, not design IP.

It also describes separate apps for mixed-signal co-simulation, multi-core simulation, distributed multi-die simulation, and functional safety. Cadence states that the Safety App is ISO 26262 certified. That certification was not rechecked against a certificate. License contents and which apps are included were not confirmed.

Technical capabilities

  • Functional simulation

    Logic simulation for the languages and flows named on the Xcelium page.

Lifecycle and categories

Lifecycle stages
Functional verification
Solution categories
Simulation

Related solutions

Siemens Questa One

Formal Verification

Siemens Questa One is a verification suite whose page names simulation, debug, static, and formal engines. Individual engines are not separated here.

View solution

Synopsys VCS

Simulation

Synopsys VCS is a functional-verification simulator with SystemVerilog and UVM support, coverage, and debug integration. It is an EDA tool, not design IP.

View solution

Related events

Explore promotion options