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Cadence Tempus Timing Solution

The Tempus page describes static timing analysis for FinFET designs, including distributed STA, SmartScope, and mixed-signal STA through the Virtuoso database.

Solution category: Timing

View Official Source Browse Timing

Overview

Cadence Tempus is a static timing signoff tool integrated with Innovus, Quantus, and Voltus. It is an EDA tool, not a DRC or LVS tool.

Cadence states that Tempus is fully certified down to 3nm. That certification was not rechecked against a foundry certificate, and the page does not say every analysis mode is certified at 3nm. Runtime and power claims on the page were not remeasured.