Public source

Cadence Pegasus Physical Verification

The page reviewed on 25 October 2026 describes the Pegasus Verification System as a physical-verification signoff flow for full-chip DRC.

Solution category: DRC & LVS

View Official Source Browse DRC & LVS

Overview

Those are named separately.

Cadence states up to 10X on DRC runs. That figure is provider-stated and was not remeasured. The same page describes the Physical Verification System (PVS) and iPegasus as performing DRC and layout-versus-schematic checks with foundry rule decks. Assura is described separately for mature nodes. A DRC result for Pegasus is not recorded as an LVS result for PVS. Supported foundries are not listed as a complete set.