Silicon Showcase⁠™

Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

Synopsys Fusion Compiler

The Fusion Compiler page describes a single RTL-to-GDSII architecture and says signoff timing, parasitic extraction, and power analysis are built in.

View Official Source (opens in a new tab)Browse Synthesis

Overview

Synopsys Fusion Compiler is an RTL-to-GDSII implementation system with one data model and built-in signoff timing, extraction, and power analysis. It is an EDA tool, not a foundry process.

It does not list supported process nodes. A foundry’s process design kit and the exact signoff deck still need confirmation. PrimeTime is a separate timing-signoff listing.

Technical capabilities

  • RTL-to-GDSII implementation

    Synthesis and physical implementation in one system, as described by Synopsys.

Lifecycle and categories

Solution categories
SynthesisPhysical Design

Related solutions

2nm Design Platform

Physical Design

Alchip’s 2nm Design Platform is an ASIC physical-design methodology for 2nm compute dies and chiplet packaging, not a foundry process node.

View solution

Cadence Genus Synthesis Solution

Synthesis

Cadence Genus is a logic and physical synthesis tool that integrates with Innovus. It is an EDA tool, not a foundry process.

View solution

Cadence Integrity 3D-IC Platform

Physical Design

Cadence design platform for planning, implementing and analyzing 2.5D and 3D multi-die / chiplet systems.

View solution

Related events

Explore promotion options