
NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The Modus page describes DFT insertion, ATPG, memory BIST, logic BIST, and single- and multi-die diagnostics.
It is an EDA tool, not automated test equipment.
Cadence states test-time reduction of up to 3X and compression beyond 400X. Those figures are provider-stated and were not remeasured. The page does not describe an ATE system. Which of the named features are in a given configuration needs confirmation.

