Silicon Showcase⁠™

Your shortlist

Nothing saved yet.

Save a solution from IP Finder, a solution listing, a solution page, or a provider’s solutions to compare it here.

Saved in this browser. Information is based on published sources. Confirm suitability and configuration with the provider.

Public source

Synopsys TestMAX

The TestMAX page describes DFT logic inserted in RTL, hierarchical ATPG compression, physically aware diagnosis, logic BIST, memory self-test and repair, and analog fault simulation.

View Official Source (opens in a new tab)Browse DFT

Overview

Synopsys TestMAX is a design-for-test family covering testability analysis, ATPG compression, logic BIST, memory self-test and repair, and analog fault simulation. It is an EDA tool, not automated test equipment.

It links the flow to the Synopsys digital design tools. It does not describe an ATE system or a probe card. Which TestMAX products are in a particular configuration needs confirmation.

Lifecycle and categories

Lifecycle stages
Synthesis and DFT
Solution categories
DFT

Related solutions

Cadence Modus DFT

DFT

Cadence Modus is design-for-test software for scan, compression, memory BIST, logic BIST, ATPG, and diagnostics. It is an EDA tool, not automated test equipment.

View solution

Related events

Explore promotion options