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CoreTSE_AHB

Full duplex is documented at 10 Mb/s, 100 Mb/s, and 1 Gb/s, and half duplex at 10 Mb/s and 100 Mb/s.

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Overview

CoreTSE_AHB is triple-speed Ethernet MAC IP for supported Microchip FPGAs, with an AMBA AHB initiator and an integrated DMA engine. The PHY stays external, through G/MII or a ten-bit interface. This is not the CoreTSE configuration, which does not document that AHB and DMA path. Both cores are included in the CoreTSE_AHB license.

The page names transmit and receive FIFOs, MDIO, Wake-on-LAN magic-packet detection, statistics counters, jumbo frames, VLAN-tagged frames, and IEEE 802.3x pause. The ten-bit interface is described for 1000BASE-X. No Ethernet line rate above 1 Gb/s is documented. FIFO depths and the supported FPGA families need confirmation.

Technical capabilities

  • Controller IP

    Digital MAC with DMA. The external PHY is not included.

  • Finder function

    Ethernet MAC

  • Implementation target

    Supported Microchip FPGAs

  • Configuration checks

    Confirm the AHB system, DMA buffers, and FPGA family. Keep this distinct from CoreTSE.

  • Recorded aliases

    CoreTSE_AHB; CoreTSE AHB

Lifecycle and categories

Solution categories
Ethernet IP
Compatibility
Pricing, licensing, and configuration availability require provider confirmation. Source

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