
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
The provider page documents Ethernet MAC configurations at 1 Gb/s, 2.5 Gb/s, 5 Gb/s, 10 Gb/s, 25 Gb/s, 40 Gb/s, 50 Gb/s, and 100 Gb/s.
CORE, MTL, and AXI variants provide different application interfaces. The PHY is separate. Silicon Showcase™ reviewed the page on 2 November 2026. Pricing, license terms, process support, and the exact configuration available for a design are not stated on the reviewed page and require confirmation from the provider.
Published as design IP
Licensable Ethernet MAC design IP.
Controller IP
Digital MAC. The analog PHY is not included.
Finder function
Ethernet MAC
Recorded aliases
DesignWare XLGMAC; dwc_ether_xlgmac
Algo-Logic ULL 10GE MAC + PHY is licensable ultra-low-latency 10 Gigabit Ethernet MAC/PHY soft IP for FPGA platforms. The official product page and FPGA IP Cores portfolio list IEEE 802.3-oriented MAC features with Avalon-ST/AXI4-Stream interfaces.
View solutionAtomic Rules UDP Offload Engine is licensable UDP/IPv4 FPGA IP. The official page states RFC 768/791 hardware offload for 10–400 GbE line rates with Avalon and AXI4 interfaces.
View solutionLicensable design IP. Ethernet MAC for 10 Mb/s, 100 Mb/s, and 1 Gb/s, with an external PHY.
View solutionLicensable design IP. Soft Ethernet controller for 10 Gb/s, 2.5 Gb/s, and 1 Gb/s, including MAC, PCS, and DMA functions.
View solutionChevin 10/25/40/100G MAC/PCS is licensable low-latency Ethernet MAC and PCS IP for FPGA/ASIC-oriented designs. The official page states IEEE 802.3by compliance and flexible licensing.
View solutionComcores Ethernet Controller is licensable ASIC-proven network interface IP. The official page states 10M–10GbE speeds with integrated DMA, timestamping, flexible host interfaces, and RTL deliverables.
View solution
