Synopsys DDR5/4 Controller IP

It says the controller connects to the Synopsys DDR5/4 PHY or other PHYs through a DFI 5.0 interface, and that configuration registers are accessed through an AMBA 3.0 APB interface. The page lists a multiport Arm AMBA AXI host interface or a single-port host interface, and it describes ECC as optional. Provider-stated latency is as low as 8 clock cycles; that figure was not remeasured. The page also describes a secure-controller configuration with an Inline Memory Encryption module. That module is not a separate listing. No exclusive DDR generation is stored, because the page names both DDR5 and DDR4. License terms are not stated on the page reviewed.