NOV172026
Conference
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Digital Blocks AXI DMA Controller IP
The AXI DMA Controller IP Cores page reviewed on 12 November 2026 describes multi-channel scatter-gather DMA for AMBA AXI4 and AXI5 systems in SystemVerilog RTL, 1 to 126 channels per instantiation, and 64- to 1024-bit data paths.
- Solution category: Memory Controllers
- Offering type: Product
Overview
Product family includes Configurable AXI4 DMA (DB-DMAC-MCn-AXI4-Config), High-Throughput AXI4 DMA (DB-DMAC-MCn-AXI4-HT), High-Throughput AXI5 DMA (DB-DMAC-MCn-AXI5-HT), and Fixed-Channel AXI4 DMA (MC2/MC4/MC8/MC16). Shared features include 32-byte descriptor nodes, memory/peripheral transfer types, unaligned transfers, per-channel interrupts, optional parity, and technology-independent RTL for ASIC and FPGA. HT variants emphasize address-ahead writes, reserved read space, up to 16 outstanding reads/writes per channel, and 2-cycle descriptor-node boundaries; AXI5-HT adds unique IDs, read data chunking, Busy/QoS Accept, WriteZero, and up to 1024-bit data. Deliverables list synthesizable SystemVerilog RTL, SDC/filelists/lint, self-checking test bench with AXI protocol checkers, C++ cycle model, bare-metal and Linux drivers, and documentation set. Measured throughput tables compare AXI4 vs AXI4-HT engines in RTL simulation. Official product page confirms licensable SystemVerilog AXI DMA IP with detailed SKUs and deliverables.
Technical capabilities
Published as design IP
Licensable semiconductor IP. This listing is not a finished controller chip.
Controller IP
Controller / protocol IP. A companion PHY is a separate listing unless the page states otherwise.
Finder function
AXI multi-channel DMA
Numbered specification: AMBA AXI4 and AXI5
AMBA AXI4 and AXI5 is named for this product on the reviewed page.
Lifecycle and categories
- Lifecycle stages
- Memory and subsystem IP
- Solution categories
- Memory Controllers
- Supported versions
- AMBA AXI4 and AXI5; 1–126 channels (fixed 2/4/8/16 options); 64–1024-bit data path options
- Compatibility
- ASIC and FPGA; AXI4/AXI5 manager ports; Linux and bare-metal drivers included. Source
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NOV192026
Workshop
SystemC Evolution Day 2026
- November 19, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative