Arasan UFS 2.1 Host Controller IP

The physical M-PHY is a separate offering.

It says UFS 2.1 introduces extensions such as multiple initiators, CMD priority for UPIUs, field firmware update using Write Buffer, and data-count updates in UPIU fields. The body says the host controller uses an M-PHY 3.1 Adapter Layer backed by a UniPro v1.6 link-layer controller, with a host-controller state machine and FIFOs, and processor access to host registers and a DMA engine over AXI or another interface. The features list names JEDEC UFS 2.0 and UFS HCI 2.0 compliance, high-performance M-PHY v3.0 type-1, 2 lanes at 5.9 Gbps per lane on that list, UniPro v1.6, boot mode, device enumeration and discovery, background operation, and secure erase and trim. Deliverables listed are synthesizable Verilog RTL, a test environment, synthesis scripts, and technical documents. Confirm UFS and HCI revisions, UniPro and M-PHY pairing, and lane rate with Arasan. Do not treat the physical M-PHY as included in this controller listing.