What It Is
Die-to-die IP is the connectivity block used between dies in one package. On the pages reviewed on 25 October 2026, Synopsys and Cadence each publish a controller and a PHY. Synopsys also publishes a combined solution that includes verification IP. The controller pages describe adapter and protocol layers. The PHY pages describe the physical signaling. Those are different listings.
An engineer looks at them when a design is split across dies and the package needs a die-to-die link. The useful comparisons on these pages are the role, the stated data rate, and the package types the provider names. Synopsys states up to 64 Gb/s for its PHY. Cadence states up to 32 Gbps per pin for its PHY, including 4, 8, 12, 16, and 24 Gbps. Neither PHY page names a UCIe revision. The controller pages do not state those PHY data rates.
The UCIe Consortium publishes the specification. This guide does not copy that specification, and it does not treat either vendor’s “latest specification” wording as a numbered revision.
Why It Matters
Teams investigating chiplets need to know whether a listing is the controller, the PHY, or a bundle, before comparing data rates or package options.
What to Watch
Ask the provider which numbered UCIe revision is implemented, which foundry and process the IP supports, whether the deliverable is controller, PHY, or both, and whether interoperability with a named second die has been shown. Silicon Showcase reviewed the vendor pages on 25 October 2026. That is not the date the providers published the pages. The consortium specifications URL responded that day; its document text was not copied here.
