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Public source

Synopsys UCIe PHY IP

Synopsys publishes this as UCIe PHY IP in the DesignWare interface-IP catalog.

Overview

Synopsys states up to 64 Gb/s and 21 Tbps/mm, and compliance with the latest UCIe specification, without naming the revision.

The page states data rates up to 64 Gb/s, bandwidth density up to 21 Tbps/mm, a 100 MHz reference clock, and support for silicon interposer, silicon bridge, RDL fanout, organic substrate, and laminate. Synopsys also states that this compliance supports interoperability between heterogeneous dies. That sentence is not confirmation that a named second product interoperates. Foundry and process availability need confirmation. This listing is the PHY, not the controller.

Technical capabilities

  • PHY IP

    Physical layer. The controller is a separate listing.

  • Stated data rate

    Provider-stated maximum on this PHY page: up to 64 Gb/s and 21 Tbps/mm. The page does not state that this rate is available in every process, package, or configuration.

Lifecycle and categories

Solution categories
UCIe IP

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