
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Synopsys publishes this as UCIe Controller IP in the DesignWare interface-IP catalog.
The provider page does not state a data rate or a numbered UCIe revision.
The page says the controller includes the die-to-die adapter and protocol layers, with AXI, CXS, CHI C2C, PCIe, CXL, and streaming interfaces, an RDI interface to the PHY, and FDI between the adapter and protocol layers. It describes single-module and multi-module configurations for advanced and standard packages, plus retry and CRC or parity checks. The page does not name a UCIe revision, a data rate, or a foundry process. It is not the PHY listing and it is not verification IP. Interoperability with another vendor’s die is not stated on this page.
Cadence UCIe Controller is design IP for the die-to-die adapter and protocol layers. The controller description does not state a data rate or a numbered UCIe revision.
View solutionCadence UCIe PHY is design IP for the die-to-die physical layer. Cadence states up to 32 Gbps per pin, including 4, 8, 12, 16, and 24 Gbps. The page does not name a UCIe revision.
View solutionEliyan NuLink PHY is licensable die-to-die and chip-to-chip interconnect PHY IP. The official products page states support for industry standards including UCIe and BoW on standard and advanced packaging.
View solutionPortfolio listing: Synopsys UCIe IP is the combined controller, PHY, and verification IP solution. It is not a separate controller or PHY. The solution page does not name a numbered UCIe revision, and a data rate on the PHY page is not a rate for this portfolio or for every process and configuration.
View solutionSynopsys UCIe PHY IP is DesignWare die-to-die PHY IP. Synopsys states up to 64 Gb/s and 21 Tbps/mm, and compliance with the latest UCIe specification, without naming the revision.
View solution
