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Eliyan NuLink Die-to-Die PHY IP (UCIe/BoW)

The Products page reviewed on 12 November 2026 describes NuLink as the building block for Eliyan D2D and D2M PHY IP cores and NuLink-X for C2C IP cores, for integration into ASIC designs.

Overview

Eliyan NuLink PHY is licensable die-to-die and chip-to-chip interconnect PHY IP.

For standard packaging, NuLink-SP PHYs target organic/laminate packages with 100–130 µm bump pitch and industry standards including UCIe and BoW, plus UMI and SBD variants; a metrics table lists example NuLink UCIe unidirectional configurations at 32 or 64 Gbps/lane on 5/3/2 nm process nodes with 32 Tx+32 Rx lanes. For advanced packaging, NuLink-AP PHYs target 40–55 µm bump pitch interposers/bridges with UCIe and SBD options and example 40 Gbps/lane UCIe unidirectional metrics. NuLink-XS C2C PHYs for longer-reach PCB connections are also tabulated. NuLight optical chiplet products are separate finished chiplet offerings on the same page and are not this PHY listing. Official page clearly positions NuLink as PHY IP cores; NuLight chiplets excluded from this listing.

Technical capabilities

  • Published as design IP

    Licensable semiconductor IP. This listing is not a finished controller chip.

  • PHY IP

    Physical-layer IP. Controllers are separate listings unless the page states a bundle.

  • Finder function

    UCIe/BoW die-to-die PHY

  • Numbered specification: example rates up to 64 Gbps/lane in tables

    example rates up to 64 Gbps/lane in tables is named for this product on the reviewed page.

  • Recorded aliases

    NuLink; NuLink-SP; Eliyan UCIe PHY

Lifecycle and categories

Solution categories
UCIe IP
Supported versions
UCIe and BoW (plus UMI/SBD variants); example rates up to 64 Gbps/lane in tables
Compatibility
Standard and advanced packaging bump-pitch ranges stated; ASIC integration. Source

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