
DVCon Europe 2026
- November 17 – 18, 2026
- Munich, Germany
- Organized by Accellera Systems Initiative
Public source
Cadence publishes the UCIe controller in its design-IP catalog, on the same page as the PHY.
The controller description does not state a data rate or a numbered UCIe revision.
The page says the controller includes the die-to-die adapter and protocol layers, supports one or more PHY modules, and supports CXS, CHI C2C, AXI, PCIe, CXL, and streaming, with CRC, retry, link-state management, and parameter negotiation. The data-rate figures on the page are in the PHY feature list and are not copied onto this controller listing. This is not evidence that the controller interoperates with a Synopsys PHY.
Synopsys UCIe Controller IP is DesignWare die-to-die controller IP for the adapter and protocol layers. The provider page does not state a data rate or a numbered UCIe revision.
View solutionEliyan NuLink PHY is licensable die-to-die and chip-to-chip interconnect PHY IP. The official products page states support for industry standards including UCIe and BoW on standard and advanced packaging.
View solutionPortfolio listing: Synopsys UCIe IP is the combined controller, PHY, and verification IP solution. It is not a separate controller or PHY. The solution page does not name a numbered UCIe revision, and a data rate on the PHY page is not a rate for this portfolio or for every process and configuration.
View solutionSynopsys UCIe PHY IP is DesignWare die-to-die PHY IP. Synopsys states up to 64 Gb/s and 21 Tbps/mm, and compliance with the latest UCIe specification, without naming the revision.
View solution
