What It Is
A Cadence post dated 16 October 2026 describes a new sub-project workstream under the Open Compute Project Foundation Chiplet System Architecture. Its stated purpose is to add requirements for real-time, safety-critical physical AI to the existing FCSA baseline. Cadence and imec are named as the leaders. The post says they are not arriving with a finished specification, and that the candidate requirements are an input for discussion.
The post sets out six constraints: sensor fusion, deterministic timing, reliability and safety, security and trust, power and thermal limits, and scaling across chiplets. It says those constraints are not yet specification rules. It maps them onto architecture areas and uses functional safety as an example of mechanisms that would still have to be written, including fault containment, safety signaling, and the evidence behind a safety case. It leaves die-to-die physical and link layers with UCIe and BOW. Chiplet microarchitecture, AI models, product certification, and vendor software stacks are described as out of scope.
This is proposed standards work. A completed physical AI chiplet standard is not what the post claims to have published, and the post does not show that chiplets from two suppliers interoperate. UCIe and BOW are named as the existing homes of the physical and link layers. That statement does not assign a numbered revision to a product. The published Cadence UCIe controller and PHY are the catalog records for Cadence die-to-die IP. Those listings do not state a numbered UCIe revision, and they are not an implementation of this proposed profile.
Why It Matters
An announcement of a workstream can be read as a standard that already sets safety, security, and timing across chiplets. The post says the contract between chiplets, and the evidence for that contract, is still being defined.
What to Watch
Ask whether a requirement is an adopted FCSA rule, a proposed physical AI profile item, optional guidance, or a vendor choice. Ask which layer stays with UCIe or BOW and which layer this workstream is still discussing. Ask what evidence a supplier can show now for timing bounds, fault containment, and attestation, and whether that evidence comes from the supplier’s own tests. Ask Cadence and imec which items are still candidates. Silicon Showcase reviewed the post on 4 November 2026. The post date is 16 October 2026.
