What It Is
Foundation IP is the logic libraries, embedded memory, I/O, and non-volatile memory used as the basic blocks of an SoC. In an EE Times Current episode, Ravi Todi, executive director of product management at Synopsys, says those blocks still have to be competitive on power, performance, and area, and that an AI-era design also has to make a schedule. EE Times marks the episode as sponsored by Synopsys. The page shows the date 10.07.26, read here as 7 October 2026.
Todi describes two cost layers beyond the license. One is integration: blocks bought from several vendors still have to meet at the seams. The other is a miss that shows up late, as a respin, a yield ramp, or a missed manufacturing window. He separates large high-performance compute dies from smaller edge-AI parts. For the large dies he talks about area on dies of about 600 to 700 square millimetres, and he gives a full-layer mask set at advanced nodes as about 20 to 40 million dollars, with a respin measured in months. For edge AI he puts power and area ahead of peak performance. He also describes Synopsys logic libraries, embedded memory, I/O, non-volatile memory, and one-time programmable memory being used with its interface IP, and he says the same views are meant to move across foundries.
The episode states further Synopsys figures: customer benchmarks of about 6 to 9 percent area and about 10 to 12 percent power, an HPC kit adding about 2 to 4 percent, more than 6,000 tape-outs, and more than 10 million wafers. Todi says Synopsys is the only foundation IP provider on all four major foundries at 2 nanometres and beyond. He does not name those foundries in the episode. Silicon Showcase has not remeasured the percentages, the mask cost, the tape-out count, or the foundry coverage.
Why It Matters
A lower license price does not show whether the libraries, memory, and I/O have been used together on the foundry and node the design will actually use, or what a late integration miss would do to the schedule.